UmCLK is a versatile solution for embedded systems, which allows you to vary reference clock of UmTRX or other SDR transceivers in a flexible way with maximum performance.
UmCLK works perfect as an external 26 MHz clock source and UmTRX output signal meets GSM specification requirements thanks to high quality VCTCXO oscillator and modern fractional/integer synthesizer chip ADF4355-2 from ADI.
UmCLK also allows you to syncronize clock and 1PPS signals for up to 4 SDR transceivers from single UmCLK board and can be used as RF signal generator from 54 MHz to 4400 MHz for high quality RF/IF converters.
Hardware Features
- Onboard VCTCXO 19.2 MHz clock oscillator, tunable from Altera 5M160 CPLD via 12 bit DAC (GPSDO function)
- Controllable by onboard Atmel chip ATmega32U2
- Extremely low noise LDO DC regulators ADM7151 from ADI to get best possible specs of ADF4355-2 chip
- Five outputs of 1:4 divided frequency from Si53301 chip capable to give up to 200 MHz LVCMOS clock output
- Four 1PPM syncronization signal distribution outputs directly from CPLD chip
- Two RF signal outputs form ADI chip to make possible use UmCLK as RF signal generator from 54 MHz to 4400 MHz
- Female pinhead connector for integration with UmTRX over 16-pin flat ribbon cable to control it from host PC through UmTRX
- One 2-pin connector for power supply in preprogrammed autonomous working mode
Specification
Parameter | Value |
|---|---|
| Physical dimensions | 85 mm x 45 mm x 12 mm |
| Power Supply voltage range | +5.5V typ, +4 to +6.5 V max |
| Power Supply current, w/o CLK loads | < 550 mA |
| Power Supply current, all CLK outputs loaded | < 800 mA |
| DC regulator noise | 1.6 uV RMS (1.7 nV/sqr(Hz) from 10 kHz to 1 MHz) |
| Power Supply supression ratio (PSSR) | > 50 dB (from 10 Hz to 1 MHz) |
| Output clock frequency | programmable from 13.5 MHz to 200 MHz |
| Output radio frequency | programmable from 54 MHz to 4400 MHz |
| Logic level of clock outputs | LVCMOS 3.3V |
| Unbuffered programmable RF output power | four levels -4 dBm, -1 dBm, +2 dBm, and upto +5 dBm |
| Buffered RF output logic level | LVCMOS 3.3V |
| Operating Temperature Range | 0 to 70 °C (industrial range -40 to +85°C upon request) |
| VCTCXO frequency stability (without GPSDO) | ±50 ppb (±0.05 ppm) over 0°C to +70°C |
| Tunable frequency stability from GPSDO | ±10 ppb (±0.01 ppm) |
| Tuning DAC resolution | 12 bit, 0 to 3.3V (~0.8 mV LSB) |
| VCTCXO Aging | ±0.3 ppm/year typ |
| VCTCXO frequency tuning range | ±10 ppm min |
| Typical clock output phase noise at 26 MHz, 100Hz carrier offset | -115 dBc/Hz |
| Typical clock output phase noise at 26 MHz, 1kHz carrier offset | -130 dBc/Hz |
| Typical clock output phase noise at 26 MHz, 10kHz carrier offset | -130 dBc/Hz |
| Typical clock output phase noise at 26 MHz, 100kHz carrier offset | -155 dBc/Hz |
| Typical RF output phase noise at 800 MHz, 10kHz carrier offset | -105 dBc/Hz |
| Typical RF output phase noise at 800 MHz, 100kHz carrier | -122 dBc/Hz |
| Typical RF output phase noise at 800 MHz, 1MHz carrier | -148 dBc/Hz |
| Typical RF output phase noise at 2500 MHz, 10kHz carrier offset | -95 dBc/Hz |
| Typical RF output phase noise at 2500 MHz, 100kHz carrier offset | -115 dBc/Hz |
| Typical RF output phase noise at 2500 MHz, 1MHz carrier offset | -140 dBc/Hz |
| Integrated jitter at RF output | < 0.5 pS RMS |
| Additive jitter at clock outputs | 100 fS RMS |
