UmTRX Hardware Updates

v2.2 of UmTRX has gone in to manufacture and with v2.3 to follow soon after.

The Fairwaves engineering team have been hard at work updating the UmTRX hardware platform, based on feedback from customers and experiences gained with deployments in the field. The first new update is v2.2, this has just gone into manufacture and changes from v2.1 include:

• Corrected component footprint for temperature sensors
• Corrected mask-to-silk warnings around T1-1, T1-2
• Mounting holes more accurately aligned to 0.5mm grid and diameters increased to 3.2 mm
• Added extra hole between LMS at centre line of board for better mounting to heatsink
• All free space of bottom layer filled by the GND copper polygon for better heat dissipation
• Add silkscreen on the vias which are under the LMS6002D ICs to make the screen stronger
• Added one more screw in the middle of the board between LMS6002D ICs
• MCX connectors replaced by MMCX
• GND pins of SMA connectors now with thermal spokes
• Resistors R103 of LMS6002D reference voltage for ADC/DAC reduced to 51 Ohm.

Just as v2.2 goes into manufacture, v2.3 is about to go into testing. Further changes in v2.3 include:

• Clock distributor IC changed to Si53301 in order to get clock divider for PLLs of LMS6002Ds
• Added R158 and R160 (S3 bypass) to enable use without clock I/O components
• Higher efficiency DC/DC conversion:
  • converters are now TPS54560D instead of L5973AD
  • Lower resistance power coils used
  • +6V output decreased to +5.5V
• DC/DC converters are synchronized to fixed 541.67kHz (26M/48) from FPGA after firmware start in order to minimise interference
• LMS6002D power supply and reference voltages are now from a single ultra low noise IC, HMC1060
• LMS6002D channels are now screened by a standard shield from Laird Tech
• Output stage IC changed to SBB5089Z to obtain flat gain up to 4GHz and 100mW output
• All possible components have been moved from the bottom to the top in order to get ~90% copper fill on the bottom
• PCB size shrank to 128x95mm, but still a 6 layer stack
• More reliable DIP switch used for Master-Slave clock mode control
• Single LVCMOS output of FPGA for UmSEL diversity switches control instead of LVDS
• Added four channel ADC ADS1015 to measure power amplifier control voltages via 1:10 resistive dividers
• Added two Hirose DF11CZ-8DP-2V(27) connectors for control and monitoring of two external power amplifiers

As can be seen there have been quite a number of updates!

The first batch of v2.3 boards should be ready for testing towards the end of June and we’ll be providing further details here and the GitHub repository will be updated in due course.

Andrew